(1) Field of the Invention
The invention relates to the field of integrated devices, and more specifically to a method of planarizing silicon dioxide surfaces in Integrated Circuit devices.
(2) Description of Prior Art
For planarization, a dry or wet etchback process can be used and has found wide application in the fabrication of semiconductor circuits. Chemical Mechanical Polishing (CMP) is an approach that has yielded very good planarization performance and that has been widely used. The factors that affect CMP can be classified in two groups. Chemistry related parameters include slurry type, pH value of slurry, the solid content of the slurry, slurry flow and process temperature. Mechanical related factors include polish pressure, back pressure, platen speed and pad type. With the CMP process, the step height of wafer topography can be reduced well in excess of 100 Angstrom.
For deep submicron planarization there are two major considerations. One is the filling of gaps with high aspect ratios. The other is to achieve actual global planarization.
The increasing need to form planar surfaces in semiconductor device fabrication has led to the development of a process technology known as Chemical Mechanical Planarization (CMP). In the CMP process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to increased use in the fabrication of complex integrated circuits.
A common requirement of all CMP processes is that the substrate be uniformly polished. In the case of polishing an electrical insulating layer, it is desirable to polish the layer uniformly from edge to edge on the substrate. To ensure that a planar surface is obtained, the electrically insulating layer must be uniformly removed. Uniform polishing can be difficult because several machine parameters can interact to create non-uniformity in the polishing process. For example, in the case of CMP, misalignment of the polishing wheel with respect to the polishing platen can create regions of non-uniform polishing across the diameter of the polished surface. Other machine parameters, such as non-homogeneous slurry compositions and variations in the platen pressure, can also create non-uniform polishing conditions.
The purpose of applying CMP therefore is to achieve local and global planarization. The ability to achieve good planarity is of critical importance for the process of lithography while the process of planarization must be simple to use and flexible in where, within the sequence of semiconductor manufacturing processing steps, it can be applied. It is current practice to first chemically soften the surface that is to be planarized followed by mechanical planarization of the surface.
FIGS. 1 and 2 show cross sections of a typical semiconductor structure with metal lines 10 and 20 over which a layer 16, of for instance a dielectric, has been deposited. FIG. 1 shows the cross section before planarization. As a matter of distinction two different patterns of metal line deposition are shown, that is a dense pattern of three adjacent and in close physical proximity metal lines 10 and a isolated pattern where a single metal line 20 is deposited whereby no other metal lines are in its proximity. It is clear from the profile of the surface of deposition 12 that planarization aspects differ between the surface of layer 12 that is above the dense pattern of metal lines 10 and the surface of layer 12 that is above the single metal line 20. of special concern is the planarization of the area 16, in between these two different patterns of metal lines, since in this area 16 the deposition 12 exhibits a deep and wide curving inward of its surface, whereby the lowest point of this curving inward may be difficult to reach when planarizing layer 12.
FIG. 2 shows a cross section that clearly demonstrates the result of the planarization process. Especially noteworthy in this cross section is the area 18 where, due to CMP dishing, the surface of layer 12 (FIG. 1) curves inward resulting in a not planar layer in area 18 (FIG. 2). The "dishing" of the surface in the region 18 represents poor planarization and is, from a semiconductor manufacturing point of view, highly undesirable.
Current planarization practice is highlighted in FIGS. 3 and 4. FIG. 3 shows a cross section where a pattern 22 of photo resist or polysilicon is deposited, this pattern serves as a mask that buffers the etching of layer 16 that is covered by pattern 22. Pattern 22 is a reverse mask pattern of the pattern of metal lines 10. The results obtained after etching are shown in the cross section presented in FIG. 4. It is clear from the cross section that surfaces 26 and 28 do not meet the requirement of good planarity due to the resulting protruding spikes 30. Further disadvantages of this reverse mask etching and planarization approach is that the process has acquired added complexity and cost while it also requires the use of a reverse mask.
U.S. Pat. No. 4,665,007 (Cservak et al.) shows a planarization method using a polymer (positive tone imaging) to fill valleys and CMP the polymer and oxide. This patent uses a positive-image polymer in contrast to the invention's negative-image polymer (PPMS). Overall this patent is close to the invention.
U.S. Pat. No. 5,077,234 (Scoopo et al.) shows a planarization method using photoresist layers.